import V6_parameter::*;

module V6 
(

//input/output data for task_2
	input wire									A_wire,
	input wire									B_wire,

	output wire									C_wire,

//input/output data for task_3
	input wire									D,
	input wire									clk,
	input wire                                  reset,

	output reg									Out,

//input/output data for task_4
	input wire	[Size_input_reg-1:0]			A_reg,
	input wire	[Size_input_reg-1:0]			B_reg,
	input wire	[Size_input_reg-1:0]			C_reg,

	output reg	[Size_output_reg-1:0]			DATA_OUT);
//------------------------------------
	reg [Size_output_reg-1:0]					data_mult;
	reg [Size_output_reg-1:0]					data_delay;
  
  
//------------------------------------
//task_2
	assign C_wire = A_wire & B_wire;
	
	
//------------------------------------  
//task_3
	always @(negedge reset or posedge clk)
	begin: task_3
		if (!reset)
			Out                  <= 0;
		else
			Out                  <= D;
	end

//------------------------------------
//task_4
	always @(negedge reset or posedge clk)
	begin: task_4
		if (!reset)
			begin
				DATA_OUT                   <= 0;
			end
		else
			begin
				data_mult                  <= A_reg * B_reg;
				data_delay                 <= C_reg;
				DATA_OUT                   <= data_mult + data_delay;

			end
	end

//------------------------------------
endmodule